Floating gate non-volatile memories such as erasable programmable read only memories (EPROMs), electrically erasable programmable read only memories (EEPROMs), block erasable ("flash") EEPROMs, and one time programmable read only memories (OTPROMs) are becoming popular for many electronic applications such as automotive control, consumer products such as tapeless answering machines, and the like. In floating gate memories, the state of each memory cell is determined by the amount of charge stored on a floating gate. The floating gate is isolated from an underlying channel by a region of oxide. Typically, the floating gate transistor is programmed and erased by processes known as Fowler-Nordheim tunneling and hot carrier injection. Recently floating gate memory cells have been both programmed and erased by Fowler-Nordheim tunneling.
There are many alternative configurations of floating gate non-volatile memory cells. For example, some configurations known as "2T" designs use a select transistor which is separate from the floating gate transistor. However, because of the additional integrated circuit area required for such configurations, the single transistor ("1T") design has become increasingly popular. The transistor in the 1T cell has a floating gate and a control gate stack which performs the same function as both the select gate and the control gate of the 2T design.
Floating gate memory cells must be able to be programmed, erased, and reprogrammed a large number of times to be useful for typical applications. For example in present technology a commercially available floating gate memory device must be able to be erased and reprogrammed approximately 10,000 times. The effect of erasing and reprogramming, however, can create problems for storing bits in floating gate memory cells. For example, the amount of time it takes to program the memory cell may vary with the number of times the cell has been programmed, as well as by processing differences across the array.
In particular it has been observed that the distributions of programming times to achieve a desired programmed threshold voltage can vary in a roughly bimodal fashion. In this typical distribution a small number of memory cells, known as "fast programming" memory cells, can be programmed in a relatively short period of time, whereas the majority of memory cells require a longer time. The fast programming memory cells will skew the distribution of program times or may even create a bimodal like distribution. This skewed distribution creates a problem in selecting the best method of programming new values into the memory array. If the programming is performed long enough to accommodate the majority of cells, the fast programming cells will tend to become over-programmed. As used herein, an "over-programmed" transistor has a threshold voltage which is very close to zero volts and may actually be negative. When a transistor's threshold becomes negative, it acts like a programmed cell whether selected or not. For a memory architecture using a 1T bit cell, over-programming causes a bit line failure.
One known technique accounts for the low threshold voltages by applying high voltages to slowly bring the threshold back to within the desired range. Such a technique is taught in U.S. Pat. No. 5,357,476, entitled "Apparatus and Method for Erasing a Flash EEPROM," invented by Clinton C. K. Kuo et al. The memory disclosed in this patent used floating gate transistors with low threshold voltages to represent the erased state. Since all transistors within a block were simultaneously erased with the same pulses, selecting the erasure sequence according to the characteristics of the majority of transistors and then selectively correcting the over-erased cells was advantageous. However, some memories now use the low threshold voltage to be the programmed state. What would be desirable therefore is a technique and a non-volatile memory using such a technique which prevents over-programming before it occurs. Such a technique and a non-volatile memory using that technique is provided by the present invention, whose features and advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.